1. Field of the Invention
The present invention relates generally to the isolation of intra-polycrystalline silicon structures, and more specifically to integrated circuit devices, including thin film transistor (TFT) structures.
2. Description of the Prior Art
Sufficient isolation between adjacent active components in a polycrystalline silicon layer of an integrated circuit device is often critical to the proper electrical function of the device. Insufficient isolation may cause a variety of problems, including leakage current and potential electrical shorts between such intra-polycrystalline silicon layer components. And, if the device is stressed by environmental factors such as high-voltage or high-radiation, isolation becomes more of a concern.
In the manufacture of polycrystalline silicon devices, it is common in the art to utilize a patterning and dry etching process to remove selected portions of a polycrystalline silicon layer between adjacent intra-polycrystalline silicon components. Due to factors such as poor etch selectivity, small amounts of polycrystalline silicon, known as stringers in the processing art, may be left behind. Stringers can contribute to leakage current and electrical shorting between adjacent intra-polycrystalline silicon components. Attempts to eradicate stringers by deeper etching has proved only partially successful, due to selectivity problems, and overetching can cause punch-through or puncturing of underlying layers. Additionally, dry etching of polycrystalline silicon layers may adversely affect device topography and therefore device planarity.
The dry etch problems described above are exacerbated for thin film transistor (TFT) devices which lend themselves to high density, high speed applications, such as video display chips for flat-screen applications. For TFT devices, isolation and planarity are especially desirable characteristics. However, current methods for manufacturing TFT devices call for the patterning and etching of various polycrystalline silicon layers, which can result in insufficient device isolation and undesirable device topography. For example, patterning and then etching the third polycrystalline silicon layer of a three polycrystalline silicon layer device may not completely remove the third polycrystalline silicon layer, leaving behind stringers of the third polycrystalline silicon layer. Such stringers would adversely affect isolation between adjacent third polycrystalline silicon layer components.
As a result of the well known problems associated with patterning and etching polycrystalline silicon layers in the manufacture of integrated circuit devices, including TFT devices, it would be desirable to utilize a method which patterns a polycrystalline silicon layer and then removes the desired portion of that polycrystalline silicon layer. Such a method would enhance device isolation.